The goals of integrated circuit design are not only to create a nominal circuit design that meets some predetermined specifications, but also to ensure that the circuit design can be manufactured reliably. Numerous sources of variation may cause some instances of a manufactured circuit design (e.g., fully simulated or fabricated microchips) to fail, that is, to not achieve at least one of the predetermined specifications. (Quite often, “testing” actually refers to full simulation prior to actual fabrication; that nomenclature is adopted in this description for simplicity.) Designers therefore seek to model such variation to estimate and reduce the susceptibility of manufactured designs to such failure.
Many methodologies fix modeling variation are known in the art, including but not limited to those described in the related applications previously incorporated by reference. Once an acceptably accurate variation model or “performance model” for a manufacturing process has been established, a number of Monte Carlo test samples may be selected according to the performance model and simulated to determine if particular design instances will fail. Even with recent advances in simulation technology however, performing a large number of Monte Carlo simulation runs of a design may still be computationally expensive.
When the performance model is sufficiently accurate, the design for manufacturability problem often shifts from estimating a yield to determining if the yield is above or below a yield target with a particular level of confidence. Monte Carlo simulation is therefore often used with a significance test, to check if a design's yield is above or below a particular yield target y with a confidence level c. Higher confidence levels denote an increased sureness that a particular outcome is not due to chance.
When a yield target is high, verifying the yield requires a large number of samples when the actual yield is above or only slightly below the target yield. For example, a three-sigma Gaussian process corresponds to only a 0.13% probability of a failure occurring. Thus, because failures are so rare for such processes, many samples that do not fail will occur before one that does fail. If the actual yield of a manufactured design is one, so no failures ever actually occur, verifying that the yield exceeds the three-sigma level, e.g., 99.87%, requires the following approximate number of samples for the confidence levels shown:
CONFIDENCE LEVELNUMBER OF SAMPLES80%120090%170095%2200
Thus, there is a need for an improved approach to reducing the number of Monte Carlo simulation samples required to compare a yield to a target yield with a particular confidence. Accordingly, the inventors have developed a novel way to help circuit designers and design tool vendors address this issue.